1. Field Of The Invention
The invention relates to dynamic semiconductor memory cells with random access (RAM=random access memory) and somewhat more particularly to such RAM memory cells which include a first polysilicon plane applied insulated on a semiconductor body as a memory electrode and a second polysilicon plane applied insulated from the first polysilicon plane as word lines and to a method of producing such memory cells.
2. Prior Art
The double polysilicon gate (Si.sup.2 -gate) process is generally considered as a standard process for attaining dynamic RAM memories. A typical Si.sup.2 -gate process for producing a dynamic 16 384 bit memory with random access is described in IEEE Journal of Solid State Circuits, Vol. Sc-11, (October 1976) pages 570-573.
With currently attainable structure resolution via photolithography of approximately 1.5 .mu.m, as can be derived from the Conference Volume, ISSCC, Feb. 15, 1980, Digest of Technical Papers, pages 232-233, a 256 K-dynamic RAM memory cell has already been designed and assembled. Insulation between neighboring active regions (transistors, memory capacitors, diffused zones, etc.) is presently attained by thick oxide regions with so-called LOCOS technology. The LOCOS process (i.e. local oxidation of silicon) is an insulation technique for integrated circuits with high packing density. As insulating material between active transistor regions, silicon dioxide (SiO.sub.2) is utilized. After selective deposition of an oxide and a nitride layer, a local oxidation takes place in the nitride-free zones, during which a strong lateral sub-oxidation (resulting in so-called bird beaks) and a strong laterally outward diffusion of field implantation takes place. As a result, the resulting device has a strong width dependence of the operating or cutoff voltage for narrow transistors. LOCOS techniques of this type are reported in Philips Research Reports, Vol. 26, No. 3, (June 1971) pages 157-165. With this type of insulation technique, because of the gradual transition between thick oxide and thin oxide regions (bird beaks) of approximately 0.5 .mu.m in length, minimum structural dimensions cannot be attained for insulation spacing. The minimum insulation spacing of LOCOS insulation thus is about double the bird beaks length, over and above the minimum structural dimension. This results that, for example, in a case of a 256 K-RAM memory cell, known from the earlier referenced Conference Volume, ISSCC, 1980, an additional space requirement of approximately 25% of of cell area is required.